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The present invention relates to the conversion of binary digital signals having definite bit transmission rates into pseudoternary A. In many situations in communications technology, transmitting and receiving stations are connected together by carrier-signal long-distance cables. Such a cable may, for example, comprise a coaxial pair surrounded by a plurality of symmetrical wire pairs.
Each of the, e. By center-tapping the side-circuit transformers, the eight spiral quads are imparted phantom-circuit operation. The eight phantom circuits, due to poor crosstalk characteristics as between the phantom and side circuits are typically utilized only for low-frequency transmissions, e. When establishing a digital transmission network, it is desirable to use as the transmission medium the carrier-signal long-distance cables already present.
It is possible to simultaneously transmit analog signals modulated onto a carrier on the side circuits and digital signals on the phantom circuits, in the same frequency range.
However, then, due to the poor crosstalk characteristics of the cable, the carrier-modulated analog signals are subject to distortion attributable to the digital signals. One can avoid this problem, by transmitting the digital signals at a frequency not the same as, but instead higher than the frequency range utilized for transmission of the analog signal-modulated carrier signal.
However, then a compromise must be found between, on the one hand, the increase of cable attenuation with increasing frequency and, on the other hand, the transmission-level decrease needed in the lower frequency range. On account of the transmitting properties of carrier-signal cable of the type in question, satisfactory use of the side circuits for transmission of the analog signal-modulated carrier and of the phantom circuits for transmission of the digital signals e.
If the converted-frequency PCM signal thusly employed is, for example, a pseudoternary digital signal, then such signal will exhibit a distinct spectral maximum at a frequency equal to one half the bit transmission rate of the original signal, i.
A pseudoternary signal, it will be understood, is a signal capable of assuming three distinct values, but with its three values utilized merely to convey information represented or representable by only two values, i. Such conversion of a binary signal into a pseudoternary digital signal can be implemented by means of amplitude modulation at one half the binary signal's bit transmission rate or frequency.
The carrier employed is a rectangular pulse train having a bit repetition frequency derived from and equal to one half that of the binary signal. The carrier is derived from the bit repetition frequency of the binary signal by means of a frequency divider. The pseudoternary-coded signal is applied to the first terminal pair of a double push-pull modulator.
The output signal of the modulator is likewise a pseudoternary-coded signal. This prior-art technique requires, as a preliminary, that the pseudoternary-coded input signal be split up into two unipolar pulse trains, one pulse train having only the positive amplitude values and the the pulse train only the negative amplitude values of the pseudoternary input signal.
Also, it is necessary to derive from the rectangular carrier signal a further carrier signal which is the complement or logical inversion of the first one. Last and not least, the use of a pseudoternary-coded signal as an input signal for such modulator requires means for converting the signal of actual interest, i.
Accordingly, the prior-art technique in question, which converts the frequency of the binary signal of interest to a more desirable frequency value by pseudoternary coding, involves considerable expense for implementing circuitry.
It is a general object of the invention to provide a novel means for more simply, inexpensively and directly converting a binary coded signal of interest into a pseudoternary coded signal, and most especially a pseudoternary coded signal comprised of A.
The present invention utilizes a number of considerations. It is to be noted that the amplitude-modulation technique described above does not represent the one and only way of effecting the requisite frequency conversion of the binary digital signal. In principle, use could be made of a pure encoding scheme, if a suitable encoding scheme and the means to implement it successfully could be found. By selecting a correct encoding scheme, it ought to be possible to convert, rather directly and almost in a single step, the binary coded signal of interest into a corresponding pseudoternary coded signal of higher frequency.
With such a concept in mind, an encoding scheme which I have found to be susceptible to straightforward implementation, i. Weber in the publication "Proceedings of the Zurich-Seminar ," F7. In contrast, each "1" bit of the binary signal is represented by two half-bits of the pseudoternary coded signal, the two half-bits each having a duration one half the duration of one bit of the binary signal, and each such pair of half-bits in the pseudoternary signal being of opposite polarity.
Which of these two alternative forms of representation is used for any particular "1" bit to be represented, is dependent upon the number of "0" bits occuring between successive "1" bits. If a "1" bit of the binary signal is represented by a particular half-bit combination e.
If a "1" bit is not immediately followed by any "0" bit, and instead the next bit is itself a "1" bit, the number of intervening "0" bits is considered even, and such immediately following "1" bit is represented by the same half-bit combination as its immediate predecessor "1" bit. In accordance with the presently preferred embodiment of the invention, such an encoding scheme is physically implemented, by applying the binary signal to be converted to the input of a clocked pulse former stage.
The pulse former stage serves to establish definite phase relationships between a modified version of the binary signal and the clock signal employed. The output signal of the pulse former stage is applied to a logic-gate circuit and also to a control signal circuit.
The latter responds to the number of bits of predetermined value in the binary signal and produces a control signal dependent thereon. The control signal is fed to the logic gate circuit, and the latter, in dependence upon the control signal, converts the binary signal which it receives into the desired pseudoternary coded signal. By developing the pseudoternary coded signal in this way, use can be made of a relatively small number of elementary circuit components.
The novel features which are considered as characteristic for the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.
The circuit configuration depicted in FIG. The first output A of pulse former stage I is connected to one input of gating circuit III, whereas the second output B of pulse former stage I is connected to the input of control signal generating stage II. The latter produces at its output C a control signal, which is applied to a second input of gating stage III to control the operation of the latter. The signal input S of pulse former stage I receives a binary coded signal which is to be converted into pseudoternary coded form.
The clock input T of clocked pulse former stage I receives a clock signal having the form of a binary rectangular pulse train. The pseudoternary coded version of the binary input signal is produced at the output F of gating circuit III, it comprises A. The signal input S is connected to the first data input of flip-flop 1, and the clock input T is connected to the clock signal input of the flip-flop.
The second input of EX-OR gate 2 is in permanent receipt of a logical "1" signal, whereas the second input of EX-OR gate 3 is in permanent receipt of a "0" signal. The second output of flip-flop 1 is connected to the first input of a NAND-gate 4 which, along with a flip-flop 5 discussed below, forms the control signal generating stage II of FIG.
The output of NAND-gate 4 is connected to the clock signal input of flip-flop 5. The second output of flip-flop 5 is connected to the first data signal input thereof. The outputs D, E of the latter are connected to respective end terminals of the primary winding of an output transformer 10, across whose secondary winding the pseudoternary coded signal sought appears, at F.
Clock pulses T are applied to the clock signal input of flip-flop 1. The positive-going or leading flank of each clock pulse causes the present logic value "0" or "1" of the input binary signal S to be registered at the first output A of flip-flop 1, with the logical complement thereof being registered at the second output of flip-flop 1.
As shown in FIG. The purpose of the clocked pulse former stage I is to establish a rigid phase relationship between the binary input signal and the clock pulse train. Looking ahead to the pseudoternary output pulse train F, and comparing it to the phase-synchronized version A of the input binary signal S, the following will be noted.
Each "0" bit of binary signal A is represented, in the pseudoternary coded signal F, by the ternary logic level "0". Each "1" bit of the binary signal A is represented, in the pseudoternary signal F, by an A. Whereas each "0" bit of the pseudoternary signal F has a duration simply equal to the period of the clock pulse train T, each two half-bits of the ternary signal F each have a duration equal to one half the period of clock pulse train T.
In the illustrated sequence of bits of input signal S and the phase-synchronized version A thereof, the first bit is a "0", and is represented in signal F by ternary level "0". The third bit of the binary signal A is a "0" and is represented in signal F by ternary level "0". It will be seen that, if the pseudoternary coded signal F is passed through a rectifier i. If a particular "1" bit of binary signal A had been immediately preceded by an even number of "0" bits, then such "1" bit is represented by the same combination of ternary levels as was used to represent the most recently preceding "1" bit of binary signal A.
If a particular "1" bit of binary signal A has been immediately preceded by an even number of "0" bits, then such "1" bit is represented not by the same combination of ternary levels as was used to represent the most recently preceding "1" bit of signal A, but instead is represented by the other of the two possible representations.
This represents the first "0" bit of binary signal A. The next bit of signal A is a "0", and is represented, in signal F, by ternary level "0", as are all "0" bits of signal A. This second "1" bit of signal A was immediately preceded by only a single "0" bit in signal A, i. This third "1" bit of signal A was immediately preceded by no "0" bit in signal A; this is to be considered an even number of "0" bits. Therefore, the third "1" bit in signal A is represented, in signal F, by the same half-bit combination as was used to represent the preceding "1" bit of signal A.
In particular, each "1" pulse of clock pulse train T results in a "1" pulse of equal duration at the output of EX-OR-gate 3, because the lower input of gate 3 is in constant receipt of a "0" signal.
In contrast, each "1" pulse of clock pulse train T results in a "0" pulse of equal duration at the output of EX-OR-gate 2, because the upper input of gate 2 is in constant receipt of a "1" signal. In the particular circuit depicted in FIG. In this way, it can be assured that the clock pulse train produced at the output of gate 3 and the inverted version thereof produced at the output of gate 2 will exhibit identical time delays relative to the clock pulse train T applied to the clock-signal input of flip-flop 1.
As already stated, the pseudoternary coded output signal F is composed from the two pulse trains D and E shown in FIG. In order that the leading and trailing flanks of the pulses in trains D and E, and especially of the half-bit-duration pulses, perfectly join each other in the formation of pulse train F, the two EX-OR-gates 6, 7 are, like gates 2, 3, preferably provided on a shared integrated-circuit substrate. NAND-gate 4 receives at its lower input the clock pulse train T i.
In particular, if a "0" bit of binary signal A is immediately followed by one or more "1" bits, then the "1" signal produced at the output of NAND-gate 4 in response to such "0" bit persists during such one or more subsequent "1" bits. In contrast, if a "0" bit of binary signal A is immediately followed by one or more further "0" bits, then NAND-gate 4 produces one distinct output "1" pulse in response to the first such "0" bit, another distinct output "1" pulse in response to the next such "0" bit, and so forth.
This signal changes level in response to each and every "0" bit of binary signal A, but is not responsive to the "1" bits of signal A. In particular, flip-flop output signal C assumes level "1" in response to an even-numbered "0" bit of signal A, and assumes level "0" in response to an odd-numbered "0" bit of signal A. The second illustrated "0" bit of signal A is an even-numbered bit, and signal C responds to it by assuming binary level "1", and persists at level "1" until the next "0" bit of signal A.
The third illustrated "0" bit of signal A is an odd-numbered bit, and signal C responds to it by assuming binary level "0". The fourth illustrated "0" bit of signal A is an even-numbered bit, and signal C responds to it by assuming binary level "1", and persists at level "1" until the next "0" bit of signal A. When signal C is at binary level "0", the two EX-OR-gates 6, 7 merely transmit to their respective outputs the pulse trains which they respectively receive at their lower inputs.
When signal C is at binary level "1", the two EX-OR-gates 6, 7 transmit to their respective outputs inverted versions of the pulse trains which they receive at their respective lower inputs. Thus when flip-flop output signal C is a "1", the lower input of gate 8 receives the clock pulse train T and the lower input of gate 9 the inverted version thereof, and vice versa when signal C is at level "0".
The upper inputs of the two NAND-gates 8, 9 both receive the binary signal A to be converted into pseudoternary coded form. During each "1" bit of binary signal A, pulse trains D and E each drop down to binary level "0" for one half the duration of the "1" bit of signal A.
Sometimes pulse train D drops down to "0" level during the first half of such "1" bit of signal A, with pulse train E dropping down to "0" level during the second half of that "1" bit; other times, pulse train E drops down to "0" level during the first half of the "1" bit of signal A, with pulse train D dropping down to "0" level during the second half of that "1" bit.
Which of the two signals D, E drops down to "0" level during which half of each "1" bit of signal A is determined by whether the most recently preceding "0" bit of signal A was an odd- or even-numbered "0" bit. These pairs of half-bit-duration "0" pulses of pulse trains D, E are combined by output transformer 10 to form the pseudoternary output signal F, already described.
As will be seen in FIG. Thus, in actuality, the circuit is not dependent upon the total previous history of its own operation, but instead upon a much shorter interval of its previous history.
Accordingly, if, for any reason, a bit error occurs in any of the intermediate binary pulse trains involved, the consequences of such error will not persist indefinitely. It will be understood that each of the elements described above, or two or more together, may also find a useful application in other types of circuits and procedures differing from the types described above.
While the invention has been illustrated and described as embodied in particular circuit configurations used to implement the conversion of a binary coded input signal into a pseudoternary coded version thereof in accordance with a particular encoding scheme, it is not intended to be limited to the details shown, since various modifications and structural changes may be made without modifications and structural changes may be made without departing in any way from the spirit of the present invention.